Design Best Practices and Common Errors

Design Best Practices and Common Errors

This checklist is provided to help AIM's users ensure that their layouts will be fabricated as intended and to avoid the most common errors or issues encountered when submitted a design for fabrication on the MPW.

This article was created with the help of Spark Photonics who is available for help with these checks or other design related services. For additional tutorials and tips on using KLayout with AIM, please see the videos here.


This checklist is divided into two sections:
  1. Essentials: Critical to avoiding delays and errors in fabricating your layout
  2. Best practices: Suggestions from AIM to improve your layout

Essentials
  1. All test, assembly, and packaging needs have been considered for layout
    1. For help with these considerations, please see the Packaging Design Guide in the PDK and/or contact AIM’s TAP Facility
  2. Design rules have been followed (unless purposely violating a rule, which will require a waiver)
  3. Any static cells (non-PCells) used from the PDK’s APSUNY (Analog Photonics) component library have not been altered (e.g., no scaling, cell origin unchanged)
  4. KLayout users: Any static cells used from the PDK’s component library do not have a dollar sign ($) in the cell name
    1. This sometimes happens when using copy/paste or merging layouts into one file
    2. To fix it, please see these instructions which include a KLayout macro.
  5. All intended layers are present (especially on multilayered structures)
    1. For example, a grating coupler that uses both FN and SN – make sure both layers are present
  6. All waveguides, metal lines, and components are on the intended layers
  7. Dimensions of custom structures are as intended
  8. PCell parameter values are as intended
    1. If multiple people are working on the same layout, ensure everyone is using the same libraries, PCells, software version, and tech files (such as WAVEGUIDES.xml for KLayout)
  9. All waveguides are connected as intended
    1. Trace through the routes of your final cells, making sure there are no misaligned waveguides or unintentional gaps
    2. For layouts in KLayout
      1. Ensure all paths have been converted to waveguides or wireguides as appropriate 
      2. Run the Functional Layout Check by going to SiEPIC -> Functional Layout Check
      1. This check has some limitations and it may show non-existent errors, but it can be helpful in spotting waveguide connectivity issues and other layout killers.
        1. Also see this video on net tracing.
  1. Any waveguides that cross each other on the same layer use a crossing component
    1. Also try to minimize crossing FN and Si waveguides, especially in the CL band – losses can be significant (>10 dB per crossing)
  2. Waveguide widths are as intended – check at junctions between components
  3. Merge any self-intersecting shapes
  4. No custom cells have the same names as PDK cells or have PDK cell names as substrings
  5. Cell names are 120 characters or less
  6. Cell names do not contain the following character strings: “error” or “notok”
  7. Cell names only contain upper- or lower-case letters, numbers, and/or the following:
    1. - hyphen
    2. _ underscore
    3. $ dollar sign (except in cells from the PDK)
    4. . period
    5. < less than
    6. > greater than
    7. ? question mark
  8. There is a single top cell – see best practices below for recommended naming
  9. DRC has been run and any intended violations are addressed in a waiver request document
    1. If waiving errors in a layout, be sure you have viewed all the unique instances of the error so that no critical errors have been missed

Best Practices:
  1. For PCells of curved objects that let you specify the number of points, ensure the number is large enough to give good resolution but is not astronomical (a few hundred points is typically enough)
    1. Visit this page for a discussion of the number of points needed to render a circle
  2. Ensure there are not more than 8000 vertices in any single polygon
    1. Shapes made from scripts can sometimes have too many vertices for efficient processing
  3. Labels are as intended, especially if the labels will be written on the mask
    1. KLayout labeling
      1. To write your labels on the mask, use KLayout’s built-in Basic library’s TEXT object on one of the waveguide layers and/or metal layers:
      1. To write your labels only in the file but not on the mask, use the Text object from the toolbar: 
    1. Other EPDA software labeling: Refer to the specific software’s documentation
    2. Use descriptive labeling whenever possible
  1. The layout file is formatted for submission
    1. Saved as .OAS file type to reduce file size
    2. If layout was prepared in KLayout, uncheck the PCell/library box when saving, as this ensures there are no PCell or library compatibility issues when sending the layout to AIM:
    1. Has a unique file name (recommended: include your assigned design ID number, the submitter’s name, and date of submission)
    2. Has a unique top cell name (recommended: same as file name)
  1. Perform DRC and net trace checking as you go (as well as after finishing your layout), to ensure it is clean along the way



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